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International Journal of Image Processing and Vision Science

Abstract

Field Programmable Gate Array (FPGA) is an effective device to realize real- time parallel processing of vast amounts of video data because of the fine-grain reconfigurable structures. This paper presents a kind of parallel processing construction of Sobel edge detection enhancement algorithm, which can quickly get the result of one pixel in only one clock periods. The algorithm is designed with a FPGA chip called XC3S200- 5ft256, and it can process 1024×1024×8 Gray Scale Image successfully. The design can locate the edge of the gray image quickly and efficiently.

DOI

10.47893/IJIPVS.2012.1017

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