In this paper we are going to modify the column decoupled SRAM for the purpose of more reduced leakages than the existing type of designs as well as the new design which is combined of virtual grounding with column decoupling logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors the simulations were done using microwind & DSCH results
PREMKUMAR, M. and JAYA PRAKASH, CH.
"DECOUPLING LOGIC BASED SRAM DESIGN FOR POWER REDUCTION IN FUTURE MEMORIES,"
International Journal of Electronics Signals and Systems: Vol. 4:
2, Article 9.
Available at: https://www.interscience.in/ijess/vol4/iss2/9