International Journal of Electronics Signals and Systems


In most of the data processing processors to perform arithmetic functions Carry Select Adder (CSLA) is used as this is one of the fastest adders. In order to increase the overall efficiency of the processor we can reduce the area and power consumption of the CSLA of processors. Based on this premise we can modify the regular SQRT CSLA architecture as 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.





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