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International Journal of Electronics Signals and Systems

Abstract

In commercial architectures, the routing consumes most of the chip area, and is responsible for most of the circuit delay. In this paper a new technique of reconfiguring FPGA circuits is proposed. The proposed technique uses BLRB approach for reconfiguring the FPGA. By this approach the routing path is less and the overall delay required to recover from fault is very less. Whenever any fault occurs the spare is selected in such way that whichever spare is nearer is chosen for reconfiguration. By selecting the nearest spare the routing path is decreased. In this method multiple faults are reconfigured at a time and the reconfigured bits are generated.

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