In this paper we are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power & area than the existing type of designs as well as the new design which is combined of virtual grounding with read Error Reduction Logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors than the Schmitt Trigger based SRAM Designs the simulations were done using microwind & DSCH results.
KRISHNA, K. HARI and HAREESH, P.
"A NEW LOW POWER TECHNOLOGY FOR POWER REDUCTION IN SRAM’S USING READ STABILITY WITH REDUCED TRANSISTOR COUNT FOR FUTURE CACHES,"
International Journal of Electronics Signals and Systems: Vol. 4
, Article 2.
Available at: https://www.interscience.in/ijess/vol4/iss2/2