This project PDW Simulator aims at developing a simulator which can be used to test the processor in the absence of Receiver hardware. This simulates the 128 bit PDW along with the required control signals which will be generated by the receiver card ESM Processor. The 128 bit PD Word is organized as four 32 bit words. Two address bits are used to indicate the word address. A strobe is to be provided to indicate the presence of each word. The simulator is being planned to be developed using Xilinx ISE 10.1 and the simulated results are to be demonstrated on Modelsim simulator or on Xilinx simulator itself.
PRITHVI, J. MOHAN and AJAY KUMAR, D.
"IMPLEMENTATION OF MULTITRACK SIMULATOR IN FPGA FOR ESM SYSTEM,"
International Journal of Electronics Signals and Systems: Vol. 4
, Article 10.
Available at: https://www.interscience.in/ijess/vol4/iss2/10