"DESIGN AND IMPLEMENTATION OF TURBO CODER FOR LTE ON FPGA" by SANTOSH GOORU and DR. S. RAJARAM

Home > IJESS > Vol. 4 > Iss. 1 (2014)

International Journal of Electronics Signals and Systems

Article Title

DESIGN AND IMPLEMENTATION OF TURBO CODER FOR LTE ON FPGA

Authors

SANTOSH GOORU, Dept. of Electronics and Communication Engineering, Thiagarajar college of Engineering, Madurai, IndiaFollow
DR. S. RAJARAM, Dept. of Electronics and Communication Engineering, Thiagarajar college of Engineering, Madurai, IndiaFollow

Abstract

Recent wireless communication standards such as 3GPP-LTE, WiMax, DVB-SH and HSPA incorporates turbo code for its excellent performance. This work provides an overview of the novel class of channel codes referred to as turbo codes, which have been shown to be capable of performing close to the Shannon Limit. It starts with a brief discussion on turbo encoding, and then move on to describing the form of the iterative decoder most commonly used to decode turbo codes. Here, Turbo decoder uses original MAP algorithm instead of using the approximated Max log-MAP algorithm thereby it reduces the number iterations to decode the transmitted information bits. This paper presents the FPGA (Field Programmable Gate Array) implementation simulation results for Turbo encoder and decoder structure for 3GPP-LTE standard.

Recommended Citation

GOORU, SANTOSH and RAJARAM, DR. S. (2014) "DESIGN AND IMPLEMENTATION OF TURBO CODER FOR LTE ON FPGA," International Journal of Electronics Signals and Systems: Vol. 4 : Iss. 1 , Article 7.
Available at: https://www.interscience.in/ijess/vol4/iss1/7

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