In this paper a new technique is proposed based on the comparison between Conventional Transistorized Flip-flop and Data transition Look ahead D flip flop here we are checking the working of DLDFF and the conventional D Flip-flop after that we are analyzing the characteristic comparison using power & area constraints after that we are proposing a Negative Edge triggered flip-flop named as Switching Transistor based D Flip-Flop(STDFF) with reduced number of transistors which will reduce the overall power area as well as delay. The simulations are done using Microwind & DSCH analysis software tools and the result between all those types are listed below. Our proposed system simulations are done under 50nm technology and the results are tabulated below. In that our proposed system is showing better output than the other flip-flops compared here.
PRANEETHA, G. LAKSHMI and HAREESH, P.
"STDFF A PASS TRANSISTOR BASED FLIP FLOP DESIGN FOR EFFICIENT INTEGRATED CIRCUITS,"
International Journal of Electronics Signals and Systems: Vol. 3
, Article 8.
Available at: https://www.interscience.in/ijess/vol3/iss4/8