"DESIGN OF ALU-64BIT FOR HIGH SPEED USING LOGICAL EFFORT" by S.A. JYOTSNAMAYEE and M. MURALI KRISHNA

Home > IJESS > Vol. 3 > Iss. 3 (2014)

International Journal of Electronics Signals and Systems

Article Title

DESIGN OF ALU-64BIT FOR HIGH SPEED USING LOGICAL EFFORT

Authors

S.A. JYOTSNAMAYEE, E.C.E Dept., Gitam University, Visakhapatnam, Andhra Pradesh.Follow
M. MURALI KRISHNA, E.C.E Dept., Gitam University, Visakhapatnam, Andhra Pradesh.Follow

Abstract

Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.. Conventional methods use repetitive manual testing guided by Logical Effort (LE).In our work, we choose gate widths inside the circuit as parameters to be optimized in order to achieve the target delay, using LE.The main objective of the paper is to calculate the delay using VerilogHDL and synthesized the output driven by it by increasing the speed using optimized paths.

Recommended Citation

JYOTSNAMAYEE, S.A. and KRISHNA, M. MURALI (2014) "DESIGN OF ALU-64BIT FOR HIGH SPEED USING LOGICAL EFFORT," International Journal of Electronics Signals and Systems: Vol. 3 : Iss. 3 , Article 7.
Available at: https://www.interscience.in/ijess/vol3/iss3/7

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