"IMPLEMENTATION OF ROBUST ARCHITECTURE FOR ERROR DETECTION AND DATA REC" by V.V.. S.V.S RAMACHANDRAM and DANIEL N. FINNEY

Home > IJESS > Vol. 3 > Iss. 1 (2013)

International Journal of Electronics Signals and Systems

Article Title

IMPLEMENTATION OF ROBUST ARCHITECTURE FOR ERROR DETECTION AND DATA RECOVERY IN MOTION ESTIMATION ON FPGA

Authors

V.V.. S.V.S RAMACHANDRAM, Department of ECE, Pragati Engineering College, Surampalem, Kakinada, A.P, India.Follow
DANIEL N. FINNEY, Department of ECE, Pragati Engineering College, Surampalem, Kakinada, A.P, India.Follow

Abstract

Video compression is necessary in a wide range of applications to reduce the total data amount required for transmitting or storing video data. Among the coding systems, Motion Estimation is of priority concern in exploiting the temporal redundancy between successive frames, yet also the most time consuming aspect of coding. This paper presents an error detection and data recovery (EDDR) design, based on the residue-and quotient (RQ) code that is embed into ME for video coding testing applications. Based on the Concurrent Error Detection (CED) concept, this work develops a robust EDDR architecture based on the RQ code to detect errors and recovery data in PEs of a ME and, in doing so, further guarantee the excellent reliability for video coding applications. We synthesized this design using Xilinx tool.

Recommended Citation

RAMACHANDRAM, V.V.. S.V.S and FINNEY, DANIEL N. (2013) "IMPLEMENTATION OF ROBUST ARCHITECTURE FOR ERROR DETECTION AND DATA RECOVERY IN MOTION ESTIMATION ON FPGA," International Journal of Electronics Signals and Systems: Vol. 3 : Iss. 1 , Article 7.
Available at: https://www.interscience.in/ijess/vol3/iss1/7

Download

Included in

Electrical and Electronics Commons

COinS