"LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSIS" by B. DILIP, P. SURYA PRASAD et al.

Home > IJESS > Vol. 2 > Iss. 4 (2013)

International Journal of Electronics Signals and Systems

Article Title

LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY

Authors

B. DILIP, Dept. of ECE, MVGR college of Engineering, Vizianagaram, AP, IndiaFollow
P. SURYA PRASAD, Dept. of ECE, MVGR college of Engineering, Vizianagaram, AP, IndiaFollow
R. S. G. BHAVANI, Dept. of ECE, JNTU Kakinada, AP, IndiaFollow

Abstract

In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the additional resistance thereby reducing the leakage current in the path. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along with this, the other advantage with LECTOR technique is that it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques.

Recommended Citation

DILIP, B.; SURYA PRASAD, P.; and BHAVANI, R. S. G. (2013) "LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY," International Journal of Electronics Signals and Systems: Vol. 2 : Iss. 4 , Article 3.
Available at: https://www.interscience.in/ijess/vol2/iss4/3

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