Home > JOURNALS > IJESS > Vol. 2 > Iss. 4 (2013)
International Journal of Electronics Signals and Systems
Abstract
As the low density parity check codes has proved their accuracy in error correcting .considering the ldpc as reference the architecture of ldpc is studied .ldpc coding contains check nodes and variable nodes which has their memory elements respectively .so an efficient use of memory can decrease the computation time. Further the arrays of memory requirement has been decreased by making the memory global to all the nodes . ldpc is considered as a finite state machine in which each node is a state .An efficient memory utilization method has been proposed to decrease the memory utilization in the fpga.
Recommended Citation
DOSS, B. L
(2013)
"LDPC ARCHITECTURE IMPLEMENTATION BY REDUCING THE MEMORY UTILIZATION,"
International Journal of Electronics Signals and Systems: Vol. 2
:
Iss.
4
, Article 15.
Available at:
https://www.interscience.in/ijess/vol2/iss4/15
