•  
  •  
 

International Journal of Electronics Signals and Systems

Abstract

As the low density parity check codes has proved their accuracy in error correcting .considering the ldpc as reference the architecture of ldpc is studied .ldpc coding contains check nodes and variable nodes which has their memory elements respectively .so an efficient use of memory can decrease the computation time. Further the arrays of memory requirement has been decreased by making the memory global to all the nodes . ldpc is considered as a finite state machine in which each node is a state .An efficient memory utilization method has been proposed to decrease the memory utilization in the fpga.

Share

COinS
 
 

To view the content in your browser, please download Adobe Reader or, alternately,
you may Download the file to your hard drive.

NOTE: The latest versions of Adobe Reader do not support viewing PDF files within Firefox on Mac OS and if you are using a modern (Intel) Mac, there is no official plugin for viewing PDF files within the browser window.