Home > IJESS > Vol. 2 > Iss. 4 (2013)
International Journal of Electronics Signals and Systems
Volume 2, Issue 4 (2013)
Articles
Evaluation of Bag of Visual Words for Category Level Object Recognition
K. S. Sujatha, G. M. Karthiga, and B. Vinod
DESIGN APPROACHES FOR LOW POWER- LOW AREA D FLIP FLOP S IN NANO TECHNOLOGY
FAYAZ KHAN and SIREESH BABU
LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY
B. DILIP, P. SURYA PRASAD, and R. S. G. BHAVANI
VECTOR CONTROL SCHEME FOR INDUCTION MOTOR WITH DIFFERENT CONTROLLERS FOR NEGLECTING THE END EFFECTS IN HEV APPLICATIONS
M. LAKSHMISWARUPA, G Tulasi Ram Das, and P.V. RAJGOPAL
GPS NAVIGATOR FOR VISUALLY IMPAIRED
MANDAR GAUDE and VIRESH CANDOLKAR
SIMULINK/MODELSIM CO-SIMULATION AND FPGA REALIZATION OF SPWM CONTROLLER FOR THREE PHASE MULTILEVEL INVERTER
C K. AMALA MINU
DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY
B. FRANCIS, Y. APPARAO, and B. CHINNARAO
WIRELESS PATIENT HEALTH MONITORING SYSTEM
PADMAVATHI KAVURU, B. CHINNARAO, and P.M FRANCIS
A NOVEL APPROACH IN IMAGE WATERMARKING WITH DISCRETE WAVELET TRANSFORM
G. KOTESWARA RAO, V. ANURAGH, T.P. SRINIVASKAUSALYANANDAN, and R.L. PRASHANTH
A NEW LOW POWER TECHNOLOGY FOR POWER REDUCTION IN SRAM’S USING COLUMN DECOUPLING COMBINED WITH VIRTUAL GROUNDING
SHAIK AHMADSAIDULU and PADALA SRINIVAS
NOVEL GROUND BOUNCE NOISE REDUCTION WITH ENHANCED POWER AND AREA EFFICIENCY FOR LOW POWER PORTABLE APPLICATION
MOHD. ABDUL SUMER and PADALA SRINIVAS
NETWORK RECONFIGURATION IN DISTRIBUTION SYSTEM BY SOFTWARE SIMULATION FOR LOSS REDUCTION
SANJEEV KUMAR
A NEW REDUCED CLOCK POWER FLIP-FLOP FOR FUTURE SOC APPLICATIONS
MOHAMMADRAFI SHAIK and PADALA SRINIVAS
