International Journal of Electronics Signals and Systems


This paper presents the architecture of a micropipeline asynchronous digital signal processing chain coupled to non-uniformly sampled data in time. Non-uniform sampling has been proven to be a better scheme than the uniform sampling to sample low activity signals. With such signals, it generates fewer samples, which means less data to process and lower power consumption. In addition, it is well-known that asynchronous logic is a low power technology. We focus on a Finite Impulse Response filter (FIR) applied to this non-uniform sampled signal obtained from an asynchronous analog to digital converter (A-ADC). The FIR filter blocks are implemented using verilog code.



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