Semiconductor devices have rapidly advanced over the past years increasing switching(on and off) speed and density of the device, causing an increase in power consumption and power dissipation; accordingly, the issues have been considered and improved . In CMOS 0.5μm process, the designed VLSI mirror-amplifier had power dissipation of 8.41 milliwatts. This technique is changed in this paper. The biasing is done in two steps proved to be correct procedure to improve overall power consumption. Source voltage was considered as 3V for the MOSIS process technology. Layout ,simulation and electrical characterization of the design were carried out by MENTOR GRAPHICS tool and CAD tools were used for the design Holding the scaling and process unchanged at 0.5μm as the previous design, the new VLSI design had power dissipation of 4.39 nanowatts in second step by reducing the dynamic loss. Multi-die chip placement is done for fabrication. More advanced 0.35um CMOS process is used for low threshold voltage and enhanced supply voltage range. This paper presents details of the key research works, results, completed chip layout and applications of the chip.
SWAROOP, K. JAYA; SUDHARAYAPPA, M. I.; JAYAPRAKASH, CH.; and BABU, V. SURENDRA
"VERY LARGE SCALE INTEGRATION TINY CHIP WITH NANOPOWER SENSOR APPLICATIONS,"
International Journal of Electronics Signals and Systems: Vol. 2
, Article 10.
Available at: https://www.interscience.in/ijess/vol2/iss2/10