This paper introduces novel architecture for Radix-10 decimal multiplier. The new generation of highperformance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multiplier. The parallel generation of partial products is performed using signed-digit radix-10 recoding of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a new algorithm decimal multioperand carry-save addition that uses a unconventional decimal-coded number systems. We further detail these techniques and it significantly improves the area and latency of the previous design, which include: optimized digit recoders, decimal carry-save adders (CSA’s) combining different decimal-coded operands, and carry free adders implemented by special designed bit counters.
INGLE, MRUNALINI E. and PANSE, TEJASWINI
"RADIX-10 PARALLEL DECIMAL MULTIPLIER,"
International Journal of Electronics Signals and Systems: Vol. 2
, Article 4.
Available at: https://www.interscience.in/ijess/vol2/iss1/4