In this paper we propose a method for the automatic test pattern generation for detecting multiple stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. The paper describes the GA and results obtained for the ISCAS 1989 benchmark circuits.
"Generating Test Patterns for Multiple Fault Detection in VLSI Circuits using Genetic Algorithm,"
International Journal of Electronics Signals and Systems: Vol. 1
, Article 13.
Available at: https://www.interscience.in/ijess/vol1/iss2/13