International Journal of Electronics and Electical Engineering


In this paper, a novel low-power high performance pulse-triggered flip-flop using conditional pulse enhancement design method is presented. Our proposed design is Enhanced Pulse Triggered Low-power Flip Flop (EPTLFF). It design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. The EPTLFF avoids unnecessary internal node transitions to reduce power consumption. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various layout simulation results comparison between previously reported design and modified design is based on 90nm and 50nm technology. The proposed design features the best power-delay-product performance in five FF designs under comparison. Its maximum power saving compared to the conventional P-FF designs is up to 18.6%.





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