International Journal of Electronics and Electical Engineering


In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) pull-up stage. In conventional DCVSL structure these lies a drawback i.e. low-to-high propagation delay is larger than high-to-low propagation delay which could be reduced by using DCVSL-R. Using resistors in DCVSL-R structure, parasitic effects are coming into picture and it occupies more area on the chip [1]. To minimize these problems we propose a new Ultra Low Power Diode (ULPD) structures in place of resistors. This provides the minimum parasitic effects and occupies less area on the chip. Second one uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This is an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using cadence and model parameters of a 180nm CMOS process. This simulation result of the two circuits is presented and is compared. These circuits are suitable for VLSI implementation. Secondly, we proposed two new CMOS Schmitt trigger circuits. These Schmitt trigger circuits are evaluated both analytically and numerically with the sources from proposed ULPD ring oscillators. The hysteresis curves of the circuits are presented. The Schmitt triggers introduced here are most suitable for high speed applications. The proposed circuits havebeen designed in TSMC-0.18μm 1.8v CMOS technology and analyzed using spectre from cadence Design systems at 50MHz and 103MHz.





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