This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz and Q=500 provides very low cut off frequency.
Kalita, Shobhanjana; BABU, S.; and SAHU, P.P.
"DESIGN AND IMPLEMENTATION OF A HIGH SPEED CLOCK AND DATA RECOVERY DELAY LOCKED LOOP USING SC FILTER,"
International Journal of Electronics and Electical Engineering: Vol. 3:
2, Article 2.
Available at: https://www.interscience.in/ijeee/vol3/iss2/2