"DESIGN AND IMPLEMENTATION OF A HIGH SPEED CLOCK AND DATA RECOVERY DELA" by Shobhanjana Kalita, S. BABU et al.

International Journal of Electronics and Electical Engineering

Article Title

DESIGN AND IMPLEMENTATION OF A HIGH SPEED CLOCK AND DATA RECOVERY DELAY LOCKED LOOP USING SC FILTER

Authors

Shobhanjana Kalita, Department of Electronics and communication Engineering, Tezpur University, Tezpur-784028, AssamFollow
S. BABU, Department of Electronics and communication Engineering, Tezpur University, Tezpur-784028, AssamFollow
P.P. SAHU, Department of Electronics and communication Engineering, Tezpur University, Tezpur-784028, AssamFollow

Abstract

This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz and Q=500 provides very low cut off frequency.

Recommended Citation

Kalita, Shobhanjana; BABU, S.; and SAHU, P.P. (2014) "DESIGN AND IMPLEMENTATION OF A HIGH SPEED CLOCK AND DATA RECOVERY DELAY LOCKED LOOP USING SC FILTER," International Journal of Electronics and Electical Engineering: Vol. 3: Iss. 2, Article 2.
DOI: 10.47893/IJEEE.2014.1132
Available at: https://www.interscience.in/ijeee/vol3/iss2/2

DOI

10.47893/IJEEE.2014.1132

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