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International Journal of Electronics and Electical Engineering

Abstract

This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz and Q=500 provides very low cut off frequency.

DOI

10.47893/IJEEE.2014.1132

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