International Journal of Electronics and Electical Engineering


Ling Adder is an advanced architecture of Parallel prefix adders. Parallel Prefix adders are used for efficient VLSI implementation of binary number additions. Ling architecture offers a faster carry computation stage compared to the conventional parallel prefix adders. Ling adders help to reduce the complexity as well as the delay of the adder further. In many computers and other kinds of processors, adders are used not only in the Arithmetic Logic Unit (ALUs), but also in other parts of the processor. Thus the delay in adders has to be decreased as maximum as possible to make the system faster. In particular, valency or the number of inputs to a single node is explored as a design parameter. High-valency Ling adders have superior area x delay characteristics over previously reported Ling-based or non-Ling based adders for the same input size. In DSP, even the multipliers require a large number of logic gates that consumes more area, power and delay. Hence, the lookup table can be used for performing computation which requires less area. Therefore, APC and OMS are the two techniques implemented in Lookup table so as to reduce the size to one-fourth of its conventional multiplier. This proposed combination of both Lookup table Multiplier and Ling adder has a better area and delay measurement.





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