"VHDL IMPLEMENTATION OF GENETIC ALGORITHM FOR 2-BIT ADDER" by VEDAVATHI. A, MEENA. K.V et al.

Home > IJEEE > Vol. 3 > Iss. 1 (2014)

International Journal of Electronics and Electical Engineering

Article Title

VHDL IMPLEMENTATION OF GENETIC ALGORITHM FOR 2-BIT ADDER

Authors

VEDAVATHI. A, The Oxford College of Engineering , Visvesvaraya Technological University, Bangalore, India.Follow
MEENA. K.V, The Oxford College of Engineering , Visvesvaraya Technological University, Bangalore, India.Follow
GAYATRI MALHOTRA, CSG, ISRO satellite Centre Indian Space Research Organisation Bangalore, IndiaFollow

Abstract

Future planetary and deep space exploration demands that the space vehicles should have robust system architectures and be reconfigurable in unpredictable environment. The Evolutionary design of electronic circuits, or Evolvable hardware (EHW), is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under control of Evolutionary algorithms. The most commonly used evolutionary algorithm is Genetic Algorithm. The paper discusses on Cartesian Genetic Programming for evolving gate level designs and proposes Evolvable unit for 2-bit adder based on Genetic Algorithm.

Recommended Citation

A, VEDAVATHI.; K.V, MEENA.; and MALHOTRA, GAYATRI (2014) "VHDL IMPLEMENTATION OF GENETIC ALGORITHM FOR 2-BIT ADDER," International Journal of Electronics and Electical Engineering: Vol. 3 : Iss. 1 , Article 3.
Available at: https://www.interscience.in/ijeee/vol3/iss1/3

Download

Included in

Power and Energy Commons

COinS