With the fast growing of digital data exchange, security information becomes much important in data storage and transmission. Due to the increasing use of images in industrial process, it is essential to protect the confidential image data from unauthorized access. Better identification of which data is relevant to human perception at higher compression ratio is needed. In this DWT-AES processor a Reconfigurable Secure Image Coding is proposed. The prominent feature of this method is a partial encryption of key lengths of 128, 192 or 256 bits. Considerable Security level also mentioned. This paper presents the AES algorithm with regard to FPGA. However, linking these two designs to achieve secure image coding is leading.
KUMAR R, SANTHOSH; RAJ, CYRIL PRASANNA; MANJULA, Y.; and KURIAN, M.Z.
"FPGA IMPLEMENTATION OF A DWT AND AES PROCESSOR FOR SECURE IMAGE CODING,"
International Journal of Electronics and Electical Engineering: Vol. 3:
1, Article 12.
Available at: https://www.interscience.in/ijeee/vol3/iss1/12