"EARLY ESTIMATION OF DELAY IN BINARY TO BCD CONVERTOR" by D. JOTHSNA NARSIMHAM and P. LAKSHMI SAROJINI

Home > IJEEE > Vol. 2 > Iss. 3 (2014)

International Journal of Electronics and Electical Engineering

Article Title

EARLY ESTIMATION OF DELAY IN BINARY TO BCD CONVERTOR

Authors

D. JOTHSNA NARSIMHAM, Dept. of Electronics & Communication, SCET, Seetharampuram, IndiaFollow
P. LAKSHMI SAROJINI, Dept. of Electronics & Communication, SCET, Seetharampuram, IndiaFollow

Abstract

A novel high speed architecture for fixed bit binary to BCD conversion which is better in terms of delay is presented in this paper. In recent years, decimal data processing applications have grown and thus there is a need to have hardware support for decimal arithmetic. Decimal digit multipliers are having Binary to BCD conversion as the basic building block. This decimal multiplication in turn is an integral part of commercial, internet and financial based applications.

Recommended Citation

NARSIMHAM, D. JOTHSNA and SAROJINI, P. LAKSHMI (2014) "EARLY ESTIMATION OF DELAY IN BINARY TO BCD CONVERTOR," International Journal of Electronics and Electical Engineering: Vol. 2 : Iss. 3 , Article 16.
Available at: https://www.interscience.in/ijeee/vol2/iss3/16

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