In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.
KRISHNA.M, GOPALA; SANKAR.CH, UMA; S, NEELIMA.; and RAO.P, KOTESWARA
"A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER,"
International Journal of Electronics and Electical Engineering: Vol. 2
, Article 2.
Available at: https://www.interscience.in/ijeee/vol2/iss2/2