International Journal of Electronics and Electical Engineering
Article Title
Abstract
IP providers are in pressing need of a convenient means to track the illegal redistribution of the sold IPs. An active approach to protect a VLSI design against IP infringement is by embedding a signature that can only be uniquely generated by the IP author into the design during the process of its creation. a VLSI IP is developed in several levels of design abstraction with the help of many sophisticated electronic design automation tools. Each level of design abstraction involves solving some NP-complete optimization problems to satisfy a set of design constraints. In this paper, a new dynamic watermarking scheme is proposed. The watermark is embedded in the state transitions of FSM at the behavioral level.
Recommended Citation
MASTANBEE, SK.; SUSEELAMMA, G.; and ADINARAYANA, E.
(2013)
"FSM BASED DIGITAL WATERMARKING IN IP SECURITY,"
International Journal of Electronics and Electical Engineering: Vol. 2
:
Iss.
2
, Article 12.
Available at:
https://www.interscience.in/ijeee/vol2/iss2/12
