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International Journal of Electronics and Electical Engineering

Abstract

In this paper, we propose an efficient architecture based on pre-computation for Viterbi decoders incorporating Talgorithm. Through optimization at both algorithm level and architecture level, the new architecture greatly shortens the long critical path introduced by the conventional T-algorithm. The design example provided in this work decomputation overhead while maintaining decoding performancemonstrates more than twice improvement in clock speed with negligible.

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