International Journal of Electronics and Electical Engineering
Abstract
In this paper, we propose an efficient architecture based on pre-computation for Viterbi decoders incorporating Talgorithm. Through optimization at both algorithm level and architecture level, the new architecture greatly shortens the long critical path introduced by the conventional T-algorithm. The design example provided in this work decomputation overhead while maintaining decoding performancemonstrates more than twice improvement in clock speed with negligible.
Recommended Citation
Peshattiwar, Atish A. and PANSE, TEJASWINI
(2013)
"High Speed ACSU Architecture for Viterbi Decoder Using T-Algorithm,"
International Journal of Electronics and Electical Engineering: Vol. 1:
Iss.
4, Article 6.
DOI: 10.47893/IJEEE.2013.1048
Available at:
https://www.interscience.in/ijeee/vol1/iss4/6
DOI
10.47893/IJEEE.2013.1048
