This paper presents a new double pulse flip flop, which is composed of a pulse generator and latch part. DPLFF consumes less power and few transistor compare to other flip-flop. As feature size of the CMOS technology continues to scale down, leakage power has become an ever-increasing important part of the total power consumption of a chip. Double pulsed latch flip flop faster than other flip flop. This design features consumes less power. In this flip flop we modified the pulse generator to suit the circuit. The double pulse latch flip-flop has symmetric timing property. TSPICE simulation result at a frequency of 400MHz shows that proposed DPLFF consume less power compare to DPSCRFF.
Tripathi, Nishant; Kumar, Amit; Singh, Sanjay; and Yadav, Dhramjeet
"DESIGN OF A NEW DOUBLE PULSE LATCH FLIP FLOP,"
International Journal of Electronics and Electical Engineering: Vol. 1:
3, Article 1.
Available at: https://www.interscience.in/ijeee/vol1/iss3/1