This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The presimulation of ADC is done in T-Spice and post layout simulation is done in Microwind3.1. The response time of the comparator equal to 6.82ns and for Flash ADC as 18.77ns.The Simulated result shoes the power consumption in Flash ADC as is 36.273mw .The chip area is for Flash ADC is 1044um2 .
Kumar, Pradeep and Kolhe, Amit
"Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS,"
International Journal of Electronics and Electical Engineering: Vol. 1
, Article 4.
Available at: https://www.interscience.in/ijeee/vol1/iss2/4