International Journal of Electronics and Electical Engineering


In this paper, a low-power structure for shift-and-add multipliers is proposed. The architec-ture considerably lowers the switching activity of conventional multipliers. The modification to the multiplier which multiplies A by B include the removal of the shifting register, direct feeding of A to the adder, bypassing the adder whenever possible, using a ring counter instead of a binary counter and removal of the partial product shift. The architecture makes use of a low-power ring counter proposed in this work . The proposed multiplier can be used for low-power applications where the speed is not a primary design parameter.





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