"Multiplier Based On Add And Shift Method By Passing Zero" by Shambhavi S, K B ShivaKumar et al.

Home > IJEEE > Vol. 1 > Iss. 1 (2012)

International Journal of Electronics and Electical Engineering

Article Title

Multiplier Based On Add And Shift Method By Passing Zero

Authors

Shambhavi S, Department of EC, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, IndiaFollow
K B ShivaKumar, Department of TC, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, IndiaFollow
M Z Kurian, Department of EC, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, IndiaFollow
H S Jayaramu, Department of TC, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, IndiaFollow

Abstract

In this paper, a low-power structure for shift-and-add multipliers is proposed. The architec-ture considerably lowers the switching activity of conventional multipliers. The modification to the multiplier which multiplies A by B include the removal of the shifting register, direct feeding of A to the adder, bypassing the adder whenever possible, using a ring counter instead of a binary counter and removal of the partial product shift. The architecture makes use of a low-power ring counter proposed in this work . The proposed multiplier can be used for low-power applications where the speed is not a primary design parameter.

Recommended Citation

S, Shambhavi; ShivaKumar, K B; Kurian, M Z; and Jayaramu, H S (2012) "Multiplier Based On Add And Shift Method By Passing Zero," International Journal of Electronics and Electical Engineering: Vol. 1 : Iss. 1 , Article 9.
Available at: https://www.interscience.in/ijeee/vol1/iss1/9

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