"DESIGN OF CONFIGURABLE IP CORE FOR ERROR DETECTION AND CORRECTION" by AJILESH RK, ANAND K et al.

International Journal of Computer Science and Informatics

Article Title

DESIGN OF CONFIGURABLE IP CORE FOR ERROR DETECTION AND CORRECTION

Authors

AJILESH RK, National Institute of Electronics and Information Technology (NIELIT), Calicut, Kerala IndiaFollow
ANAND K, National Institute of Electronics and Information Technology (NIELIT), Calicut, Kerala IndiaFollow
NANDAKUMAR. R, National Institute of Electronics and Information Technology (NIELIT), Calicut, Kerala IndiaFollow
SREEJEESH.S. G, National Institute of Electronics and Information Technology (NIELIT), Calicut, Kerala IndiaFollow

Abstract

This paper addresses the design & implementation of configurable Intellectual Property (IP) core for double error detection and single error Correction. The encoding /decoding algorithms considered in this can be implemented with a simple and faster hardware. The block can be used for coding and decoding word having any length and correct single bit error occurred and detect double bit error, during transmission. The user can define the word length and the hamming bits required.

Recommended Citation

RK, AJILESH; K, ANAND; R, NANDAKUMAR.; and G, SREEJEESH.S. (2014) "DESIGN OF CONFIGURABLE IP CORE FOR ERROR DETECTION AND CORRECTION," International Journal of Computer Science and Informatics: Vol. 3: Iss. 3, Article 9.
DOI: 10.47893/IJCSI.2014.1144
Available at: https://www.interscience.in/ijcsi/vol3/iss3/9

DOI

10.47893/IJCSI.2014.1144

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