International Journal of Computer Science and Informatics


Virtual Fabrication of sub-40nm Bulk MOSFET is carried out under channel engineering and source drain engineering process. These structures enable more aggressive device scaling in nano-scale region because of their ability to control short channel effects. How ever during scaling the junction depth should also be scaled down, which increases parasitic resistance so silicidation technique has been applied to reduce their effects on device. Analog performance has been measured in terms of gm, gds ,Av ,fT and fmax .The simulation result predict that gm is 3.75ms for engineered MOSFET as compared to nonengineered MOSFET with gm of 2.9ms for similar gate length, similarly Av for engineered device is 17.5db and for non-engineered device is 6.96db,fT is 146GHz and for non-engineered fT is 65GHz,fmax is 299GHz for engineered device and for nonengineered device fmaxis 170GHz and a comparison of an engineered device is done with a non engineered device to investigate the improved performance of an engineered device as compared to a non engineered device. Silvaco TCAD Tool is used for Virtual fabrication and simulation. ATHENA process simulator is used for virtual fabrication and ATLAS device simulator is used for device characterization.





To view the content in your browser, please download Adobe Reader or, alternately,
you may Download the file to your hard drive.

NOTE: The latest versions of Adobe Reader do not support viewing PDF files within Firefox on Mac OS and if you are using a modern (Intel) Mac, there is no official plugin for viewing PDF files within the browser window.