This paper explores different data path architecture topologies for low power solutions. And we look at the energy optimization of different topologies. This paper is aimed at characterizing various architecture implementations of different data path operators like adders and multipliers and a different style of multiplier with minimum power and delay product and different adder topologies.
"Power Optimization For A Datapath Of General Purpose Processor,"
International Journal of Computer Science and Informatics: Vol. 1:
1, Article 13.
Available at: https://www.interscience.in/ijcsi/vol1/iss1/13