There is a wide selection of flip-flops in the literature. Many contemporary microprocessors selectively use master-slave and pulsed-triggered flip-flops. Transmission gated flip-flop, are made up of two stages, one master and one slave Alternatively, pulse-triggered flip-flops reduce the two stages into one stage and are characterized by the soft edge property. The concepts discussed in the related work are related to synchronous design’s novel method for low power dissipation asynchronous methods have been improving so as to reduce the power consumption an asynchronous methods for flip-flops are being implemented.
Raja, G. Abhinaya and Srinivas, P.
"Asynchronous Model of Flip-Flop’s and Latches for Low Power Clocking,"
International Journal of Computer and Communication Technology: Vol. 7
, Article 7.
Available at: https://www.interscience.in/ijcct/vol7/iss2/7