A new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’scomplement- based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. Moreover, depending on data switching activity statistically reduce the power consumption
Suhasini, M.; Kumar, K. Prabhu; and Srinivas, P.
"Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm,"
International Journal of Computer and Communication Technology: Vol. 7
, Article 4.
Available at: https://www.interscience.in/ijcct/vol7/iss2/4