International Journal of Computer and Communication Technology
Abstract
Multi-pattern matching is known to require intensive memory accesses and is often a performance bottleneck. Hence specialized hardware-accelerated algorithms are being developed for line-speed packet processing. While several pattern matching algorithms have already been developed for such applications, we find that most of them suffer from scalability issues. We present a hardware-implementable pattern matching algorithm for content filtering applications, which is scalable in terms of speed, the number of patterns and the pattern length. We modify the classic Aho-Corasick algorithm to consider multiple characters at a time for higher throughput. Furthermore, we suppress a large fraction of memory accesses by using Bloom filters implemented with a small amount of on-chip memory. The resulting algorithm can support matching of several thousands of patterns at more than 10 Gbps with the help of a less than 50 KBytes of embedded memory and a few megabytes of external SRAM.
Recommended Citation
Santhi, J. and Srinivas, L.
(2016)
"Fast and Scalable Pattern Matching for Memory Architecture,"
International Journal of Computer and Communication Technology: Vol. 7:
Iss.
2, Article 3.
DOI: 10.47893/IJCCT.2016.1344
Available at:
https://www.interscience.in/ijcct/vol7/iss2/3
DOI
10.47893/IJCCT.2016.1344
