Power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter, arises from it’s switching activity, which is mainly influenced by the supply voltage and effective capacitance.[1,2,3] To optimize power dissipation, the researches show various techniques like appropriate coding, appropriate design architectures, appropriate manipulation algorithms. In this paper we have applied adiabatic logic design approach to design COMS inverter. Adiabatic switching techniques based on energy recovery principle are one of the innovative solutions at a circuit and logic level achieve reduction in power  Various adiabatic logic based inverters are shown. Mainly our aim is to design and simulate PFAL inverters. Finally we have calculated dissipated power of static CMOS inverter and compare it with that of PFAL based inverter. [4, 6]
"Power Efficient VLSI Inverter Design using Adiabatic Logic and Estimation of Power dissipation using VLSI-EDA Tool,"
International Journal of Computer and Communication Technology: Vol. 3:
3, Article 2.
Available at: https://www.interscience.in/ijcct/vol3/iss3/2