DESIGN OF A HIGH INPUT-RANGE DUTY-CYCLE DETECTOR USING 180NM TECHNOLOGY
This paper reports a design of a high input-range duty-cycle detector. It is detects whether the duty-cycle of the incoming signal is more than a certain value (45 percent in this case) or not. Designed circuits form an integral part of Dutycycle detector. In this design authors have used a very simple analog current amplifier. This circuit is capable of sensing an input duty-cycle in a wide range of 0.5 to 95 percent of input clock cycle at a frequency of 833 MHz. This design has been implemented in 180 nm technology with cadence environment and its average transient power consumption is 0.6 mW at 833 MHz.